1. Field
Various features relate to an integrated device that includes a via with a side barrier layer that traverses an encapsulation layer.
2. Background
FIG. 1 illustrates a first package 102 being coupled to a second package 104. The first package 102 includes a first substrate 106, a first die (e.g., chip) 108, a mold 110, a first set of solder balls 116, and a first set of interconnects 118, and a third set of solder balls 126. The first substrate 106 may include traces and/or vias (both of which are not shown). The second package 104 includes a second substrate 105, a second die 107, a third die 109, a second set of solder balls 115, a first set of wire bonding 117, and a second set of wire bonding 119. The second substrate 105 may include traces and/or vias (both of which are not shown). The second package 104 is positioned above the first package 102.
The first die 108 is coupled to a first surface (e.g., top surface) of the first substrate 106 through the first set of interconnects 118. The mold 110 encapsulates the first die 108 and the first set of interconnects 118. The first set of solder balls 116 is coupled to a second surface (e.g., bottom surface) of the first substrate 106. The third set of solder balls 126 is coupled to the first surface (e.g., top surface) of the first substrate 106. The third set of solder balls 126 is surrounded by the mold 110. The first substrate 106 includes a set of traces and/or vias that may electrically connect to the first die 108 and/or the first set of solder balls 116.
The second die 107 and the third die 109 are coupled to a first surface (e.g., top surface) of the second substrate 105. The second die 107 is electrically coupled to the traces and/or vias of the second substrate 105 through the first set of wire bonding 117. The third die 109 is electrically coupled to the traces and/or vias of the second substrate 105 through the second set of wire bonding 119. The second set of solder balls 115 is coupled to a second surface (e.g., bottom surface) of the second substrate 105.
FIG. 2 illustrates a conventional package on package (PoP) integrated device. As shown in FIG. 2, the integrated device 200 includes the first package 102 and the second package 104 of FIG. 1. As shown in FIG. 2, when the first package 102 is coupled to the second package 104, the second set of solder balls 115 of the second package 104 is coupled to the third set of solder balls 126 of the first package 102.
One major drawback of the package on package (PoP) configuration shown in FIGS. 1 and 2 is that it creates an integrated device with a form factor that may be too large for the needs of mobile computing devices. That is, the PoP configuration shown in FIG. 2 may be too thick and/or have a surface area that is too large to meet the needs and/or requirements of mobile computing devices. In particular, there is a constant need to reduce the size of integrated devices, especially integrated device that are going to be implemented in mobiles devices. Moreover, the process of fabricating the PoP configuration can be complicated and costly.
Therefore, there is a need for a cost effective integrated package that has an improved form factor (e.g., smaller, narrower, thinner). Ideally, such an integrated package will provide higher density connections, as well being more cost effective (e.g., cheaper) to fabricate than current integrated packages.